Cfet power connection structure and the methods of forming the same

A method comprising:

• forming a lower source/drain region;
• forming a first contact etch stop layer over the lower source/drain region;
• forming a first inter-layer dielectric over the first contact etch stop layer;
• forming an upper source/drain region over the first inter-layer dielectric;
• forming a second contact etch stop layer over the upper source/drain region;
• forming a second inter-layer dielectric over the second contact etch stop layer;
• performing a first etching process to form a first contact opening, wherein the first contact opening penetrates through the upper source/drain region to reach the lower source/drain region;
• forming a first dielectric contact spacer in the first contact opening;
• forming a first contact plug in the first contact opening;
• and
• forming a second contact plug underlying and electrically connected to the lower source/drain region, wherein the second contact plug is electrically connected to the first contact plug through the lower source/drain region.

A structure comprising:

• a first transistor comprising:
• a lower source/drain region of a first conductivity type;
• a second transistor comprising:
• an upper source/drain region overlapping and spaced apart from the lower source/drain region, wherein the upper source/drain region is of a second conductivity type opposing the first conductivity type;
• a first contact plug over a first source/drain region of the lower source/drain region and the upper source/drain region;
• and
• a second contact plug under the first source/drain region of the of the lower source/drain region and the upper source/drain region, wherein the first contact plug is electrically connected to the second contact plug through the first source/drain region.