Discontinuous high dielectric constant (hk) layer

A stacked field effect transistor array comprising:

• a plurality of stacked field effect transistor structures comprising:
• a lower field effect transistor comprising a lower first drain-source region, a lower second drain-source region, and at least one lower nanosheet channel region interconnecting the lower first and lower second drain-source regions;
• an upper field effect transistor comprising an upper first drain-source region, an upper second drain-source region, and at least one upper nanosheet channel region interconnecting the upper first and upper second drain-source regions;
• a high-K metal gate structure surrounding at least a portion of the at least one lower nanosheet channel region and at least a portion of the at least one upper nanosheet channel region;
• a middle dielectric isolation region separating the upper and lower field effect transistors;
• and
• gate spacers on sides of the high-K metal gate structure;
• wherein the high-K metal gate structure includes:
• gate metal;
• and
• high-K liner material on the at least one lower nanosheet channel region, the at least one upper nanosheet channel region, and in a first wall region extending up the gate spacers next to the lower field effect transistor no further than the middle dielectric isolation region;
• and
• at least one wiring structure with a plurality of horizontal wires and a plurality of vertical contacts selectively connected to at least a subset of the gate structures and at least a subset of:
• the lower first drain-source regions, the lower second drain-source regions, the upper first drain-source regions and the upper second drain-source regions.

A method of forming a stacked field effect transistor structure, the method comprising:

• providing an initial structure comprising:
• a lower field effect transistor precursor structure comprising a lower first drain-source region, a lower second drain-source region, and at least one lower nanosheet channel region interconnecting the lower first and lower second drain-source regions;
• an upper field effect transistor precursor structure comprising an upper first drain-source region, an upper second drain-source region, and at least one upper nanosheet channel region interconnecting the upper first and upper second drain-source regions;
• a middle dielectric isolation region separating the upper and lower field effect transistor precursor structures;
• a substrate structure under the lower field effect transistor precursor structure, the substrate structure including a silicon portion and shallow trench isolation portions separated from the silicon portion by nitride layers;
• and
• gate spacers extending upward from the shallow trench isolation portions;
• depositing first high-K liner material and a cap layer on the at least one lower nanosheet channel region, the at least one upper nanosheet channel region, the middle dielectric isolation region, a portion of the substrate structure inward of the gate spacers, and the gate spacers;
• removing the first high-K liner material and the cap layer from the at least one upper nanosheet channel region, a top surface and sides portions of the middle dielectric isolation region, and portions of the gate spacers extending above the middle dielectric isolation region;
• depositing additional high-K liner material on the at least one upper nanosheet channel region;
• removing the cap layer from the bottom surface of the middle dielectric isolation region, portions of the gate spacers extending below the middle dielectric isolation region, the portion of the substrate structure inward of the gate spacers, and the at least one lower nanosheet channel region;
• depositing n-type work function metal on the at least one lower nanosheet channel region, the at least one upper nanosheet channel region, the middle dielectric isolation region, the portion of the substrate structure inward of the gate spacers, and the gate spacers;
• filling in gate metal around the at least one lower nanosheet channel region, the at least one upper nanosheet channel region, and the middle dielectric isolation region;
• removing the silicon portion of the substrate structure to create a cavity and expose an adjacent portion of the first high-K liner material and carrying out O2 annealing of the exposed adjacent portion;
• and
• depositing backside inter-layer dielectric in the cavity.