US 2026/0096145 A1 · FORKSHEET TRANSISTORS WITH WRAPPED-AROUND GATE DIELECTRIC

Abstract

Techniques are provided to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine and nanosheets with a wrapped-around gate dielectric. The dielectric spine may be formed prior to the formation of gate structures. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction. The first and second semiconductor regions may include any number of nanosheets. A dielectric spine extends in the first direction centrally aligned between the first and second semiconductor regions. The gate dielectric of the gate structures on either side of the dielectric spine is wrapped around the semiconductor regions, such that the gate dielectric is present between the nanosheets and the dielectric spine along the second direction. The dielectric spine may include a dielectric liner that itself is removed prior to formation of the gate structures, thus provided space for the wrapped-around gate dielectric.

Claims20

Dependent claims

An integrated circuit comprising:

a first semiconductor device having a first semiconductor material extending in a first direction from a first source or drain region, and a first gate structure extending in a second direction over the first semiconductor material;
a second semiconductor device having a second semiconductor material extending in the first direction from a second source or drain region, and a second gate structure extending in the second direction over the second semiconductor material, and wherein the second source or drain region is aligned with the first source or drain region along the second direction;
and
a dielectric spine extending in the first direction between the first semiconductor material and the second semiconductor material and between the first source or drain region and the second source or drain region, wherein the dielectric spine has a first width along the second direction between the first semiconductor material and the second semiconductor material and a second width between the first source or drain region and the second source or drain region that is at least 2 nm smaller than the first width.

1 more element

An electronic device, comprising:

a chip package comprising one or more dies, at least one of the one or more dies comprising
a first semiconductor material extending in a first direction from a first source or drain region;
a first gate structure extending in a second direction over the first semiconductor material;
a second semiconductor material extending in the first direction from a second source or drain region;
a second gate structure extending in the second direction over the second semiconductor material, wherein the second source or drain region is aligned with the first source or drain region along the second direction;
and
a dielectric spine extending in the first direction between the first semiconductor material and the second semiconductor material and between the first source or drain region and the second source or drain region, wherein the dielectric spine has a first width along the second direction between the first semiconductor material and the second semiconductor material and a second width between the first source or drain region and the second source or drain region that is at least 2 nm smaller than the first width.

4 more elements

Dependencies are inferred from the claim text.

Forksheet transistors with wrapped-around gate dielectric

Life of this patent

Forksheet transistors with wrapped-around gate dielectric

Life of this patent

Abstract

Claims20