Semiconductor device and methods of formation
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorTzu-Ging LIN
Life of this patent
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Abstract
Sacrificial semiconductor layers are removed from a layer stack of a semiconductor device prior to formation of inner spacers and source/drain regions of a nanostructure transistor of the semiconductor device. The sacrificial semiconductor layers may be removed along with intermixing layers that may have formed due to intermixing between the materials of the sacrificial semiconductor layers and semiconductor channel layers. The sacrificial semiconductor layers and intermixing layers may be replaced with sacrificial dielectric layers. The sacrificial dielectric layers may then be etched to form cavities in which the inner spacers are formed.
Claims20
A method, comprising:
- forming a plurality of semiconductor channel layers and a plurality of sacrificial semiconductor layers such that the plurality of semiconductor channel layers and the plurality of sacrificial semiconductor layers are arranged in an alternating manner in a direction that is approximately perpendicular to a semiconductor substrate of a semiconductor device;
- performing a first etch operation to etch the plurality of semiconductor channel layers and the plurality of sacrificial semiconductor layers to form a source/drain recess,
- wherein the source/drain recess defines a plurality of nanostructure channels that are arranged in the direction that is approximately perpendicular to the semiconductor substrate,
- wherein the plurality of nanostructure channels and the plurality of sacrificial semiconductor layers are arranged in an alternating manner in the direction that is approximately perpendicular to the semiconductor substrate;
- and
- performing a second etch operation to remove the plurality of sacrificial semiconductor layers from the semiconductor device;
- forming a plurality of sacrificial dielectric layers in spaces between the plurality of nanostructure channels previously occupied by the plurality of sacrificial semiconductor layers;
- and
- forming a source/drain region in the source/drain recess.
A semiconductor device, comprising:
- a plurality of nanostructure channels arranged in a direction that is approximately perpendicular to a semiconductor substrate of the semiconductor device;
- a gate structure wrapping around the plurality of nanostructure channels;
- a source/drain region adjacent to a side of the gate structure and adjacent to ends of the plurality of nanostructure channels;
- a plurality of inner spacers between the source/drain region and the gate structure;
- and
- a plurality of non-contiguous epitaxial regions between the source/drain region and at least one of:
- the plurality of nanostructure channels, or
- the plurality of inner spacers.
A method, comprising:
- forming a plurality of semiconductor channel layers and a plurality of sacrificial semiconductor layers such that the plurality of semiconductor channel layers and the plurality of sacrificial semiconductor layers are arranged in an alternating manner in a direction that is approximately perpendicular to a semiconductor substrate of a semiconductor device;
- forming a source/drain recess through the plurality of semiconductor channel layers and the plurality of sacrificial semiconductor layers;
- removing, through the source/drain recess, the plurality of sacrificial semiconductor layers from the semiconductor device;
- forming a plurality of sacrificial dielectric layers in spaces between the plurality of semiconductor channel layers previously occupied by the plurality of sacrificial semiconductor layers;
- forming inner spacers on ends of the plurality of sacrificial dielectric layers exposed through the source/drain recess;
- forming a plurality of non-contiguous epitaxial regions on sidewalls of the source/drain recess;
- and
- forming a source/drain region on the plurality of non-contiguous epitaxial regions in the source/drain recess.
Dependencies are inferred from the claim text.