Stacked ferroelectric random access memory

An integrated circuit (IC) die, comprising:

• a first surface and a second surface opposite the first surface;
• a first memory cell proximate the first surface comprising a first capacitor over a first transistor, the first capacitor comprising an insulating material between first and second terminals, the first transistor comprising a first source electrode coupled with the first terminal, and a first drain electrode, wherein the insulating material is a ferroelectric or an antiferroelectric material;
• a second memory cell under the first memory cell, the second memory cell comprising a second capacitor under a second transistor, the second capacitor comprising the insulating material between third and fourth terminals, the second transistor comprising a second source electrode coupled with the third terminal, and a second drain electrode;
• and
• a bit line between the first transistor and the first capacitor, wherein the bit line is coupled with the first drain electrode and the second drain electrode.

A system, comprising:

• an integrated circuit (IC) die comprising:
• a memory array comprising:
• first and second capacitors proximate a first surface, each capacitor comprising a ferroelectric or an antiferroelectric material between first and second terminals;
• a first access transistor under the first capacitor comprising a first electrode and a second electrode coupled with the first terminal of the first capacitor;
• a second access transistor under the second capacitor comprising a third electrode and a fourth electrode coupled with the first terminal of the second capacitor;
• first memory access lines over the first and second capacitors, each first memory access line coupled with one of the second terminals;
• and
• circuitry comprising a first transistor and a laterally adjacent second transistor, wherein the first access transistor is over and proximate the first transistor and the second access transistor is over and proximate and a second transistor, and the circuitry is between the memory array and a second surface opposite the first surface.