Semiconductor memory device with mold insulating layers, semiconductor patterns, and gate electrodes

A semiconductor memory device comprising:

• a plurality of mold insulating layers on a substrate and spaced apart from one another in a first direction perpendicular to an upper side of the substrate;
• a bit line that extends in the first direction on the substrate;
• a semiconductor pattern between ones of the mold insulating layers that are adjacent to each other in the first direction, wherein the semiconductor pattern contacts the bit line, and extends in a second direction parallel to the upper side of the substrate;
• a gate electrode which extends in a third direction different from the second direction and is on both side surfaces of the semiconductor pattern in the first direction;
• and
• an information storage element on the gate electrode and the semiconductor pattern, wherein the information storage element comprises a first electrode that has a U shape, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode,
• wherein the second electrode is on inner walls of the first electrode and is not on outer walls of the first electrode in the first direction.

A semiconductor memory device comprising:

• a plurality of mold insulating layers on a substrate and spaced apart from one another in a first direction perpendicular to an upper side of the substrate;
• a plurality of semiconductor patterns which are between ones of the plurality of mold insulating layers adjacent to each other in the first direction, and extend in a second direction parallel to the upper side of the substrate;
• a plurality of gate electrodes which extend in a third direction different from the first direction and the second direction, wherein each of the plurality of gate electrodes comprises a first gate electrode on a first side of a respective one of the plurality of semiconductor patterns in the first direction, and a second gate electrode on a second side opposite to the first side of the respective one of the plurality of semiconductor patterns in the first direction;
• an information storage element comprising a first electrode electrically connected to each of the plurality of semiconductor patterns, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode;
• a bit line on the substrate, wherein the bit line extends in the first direction and contacts each of the plurality of semiconductor patterns;
• and
• an insulating buffer film on a side wall of a respective one of the plurality of mold insulating layers,
• wherein the first electrode has a U shape, and
• wherein the second electrode is in an interior of the U shape of the first electrode.

A semiconductor memory device comprising:

• a plurality of mold insulating layers on a substrate and spaced apart from one another in a first direction perpendicular to an upper side of the substrate;
• a plurality of semiconductor patterns which are between respective ones of the plurality of mold insulating layers adjacent to each other in the first direction, and extend in a second direction parallel to the upper side of the substrate;
• a plurality of gate electrodes that extend in a third direction different from the first direction and the second direction, on respective ones of the plurality of semiconductor patterns;
• an information storage element comprising a first electrode electrically connected to each of the plurality of semiconductor patterns, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode;
• a bit line on the substrate, wherein the bit line extends in the first direction, and contacts the plurality of semiconductor patterns;
• and
• a plurality of insulating buffer films respectively disposed between the first electrodes that are adjacent to each other in the first direction,
• wherein the first electrode has a U shape.