High speed level shifter

A semiconductor device, comprising:

• a low voltage to high voltage level shifter structured to receive a low voltage input signal and provide a high voltage output signal, the low voltage to high voltage level shifter including a first buffer, including:
• a pulldown n channel metal oxide semiconductor (NMOS) transistor structured to receive the low voltage input signal;
• a pullup p channel metal oxide semiconductor (PMOS) transistor structured to receive the low voltage input signal;
• and
• a cutoff metal oxide semiconductor (MOS) transistor structured to receive a delayed cutoff signal;
• wherein:
• the delayed cutoff signal inversely corresponds to the low voltage input signal;
• and
• the pullup PMOS transistor, the pulldown NMOS transistor, and the cutoff MOS transistor are connected in series between a first power rail and a reference voltage rail.

An integrated circuit, comprising:

• first and second power rails, the first power rail structured to provide a first operating voltage and the second power rail structured to provide a reference voltage;
• a PMOS transistor connected to the first power rail and structured to operate at a first gate voltage, and to receive at its gate an input signal having a maximum voltage less than the gate voltage;
• a first NMOS transistor connected between the PMOS transistor and the second power rail, the first NMOS transistor structured to operate at the first gate voltage and to receive the input signal at its gate;
• and
• a second NMOS transistor connected between the first NMOS transistor and the second power rail, the second NMOS transistor structured to operate at the gate voltage and to receive at its gate an input signal having a maximum voltage equal to the gate voltage.

A method of forming a semiconductor device, comprising:

• forming a low voltage to high voltage level shifter to receive a low voltage (LV) input signal and output a high voltage (HV) output signal corresponding to the LV input signal, the low voltage to high voltage level shifter including a first buffer configured to produce an inverted HV signal inversely corresponding to the LV input signal, the low voltage to high voltage level shifter formed by:
• configuring an n channel metal oxide semiconductor (NMOS) HV pulldown transistor to receive the LV input signal;
• connecting an p channel metal oxide semiconductor (PMOS) HV pullup transistor in series between a HV rail and the pulldown transistor, the pullup transistor configured to receive the LV input signal and to cooperate with the pulldown transistor to produce the inverted HV signal;
• connecting a metal oxide semiconductor (MOS) HV cutoff transistor in series with the pulldown transistor and the pullup transistor, between the pulldown transistor and a reference voltage rail;
• and
• configuring the cutoff transistor to receive a delayed HV cutoff signal inversely corresponding to the LV input signal.