Comparator circuit

A comparator circuit, comprising:

• a first pre-amplification stage configured to switch between a reset state and a comparison state according to a clock signal, cut off an input signal and reset an output of the first pre-amplification stage to a first preset level in the reset state, and amplify the input signal to generate a first output signal in the comparison state;
• a second pre-amplification stage including a first positive feedback structure, wherein the second pre-amplification stage is configured to switch between the reset state and the comparison state according to the first output signal, amplify the first output signal in the comparison state to generate a second output signal, and provide positive feedback for the second output signal through the first positive feedback structure;
• and
• a latch stage connected to the second output signal and the clock signal, wherein the latch stage includes a second positive feedback structure and a third positive feedback structure and is configured to reset an output end of the latch stage to a second preset level according to the clock signal in the reset state, and use the second output signal and the clock signal to control the second positive feedback structure and the third positive feedback structure to be turned on to provide positive feedback for the output end in the comparison state.