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US 2026/0095159 A1Published application
Flip-flop circuit with multiple data paths
AssigneeApple Inc.
InventorsVIVEKANANDAN VENUGOPAL, QI YE, RAJIV MITTAL
Life of this patent
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Abstract
A flip-flop circuit includes a first data path configured to provide a first path inverted value of an input signal to an output node of the flip-flop circuit based on a clock pulse. The flip-flop circuit also includes a second data path configured to provide a second path inverted value of the input signal to the output node via a master latch circuit and a slave latch circuit, based on a clock signal.
Claims20
An apparatus, comprising:
- a flip-flop circuit comprising:
- a first data path configured to provide a first path inverted value of an input signal to an output node of the flip-flop circuit based on a clock pulse;
- and
- a second data path configured to provide a second path inverted value of the input signal to the output node via a master latch circuit and a slave latch circuit, based on a clock signal.
1 more element
A method, comprising:
- receiving an input signal at an input node of a flip-flop circuit;
- providing the input signal to a first data path of the flip-flop circuit, wherein the first data path provides a first path inverted value of the input signal to an output node of the flip-flop circuit based on a clock pulse;
- and
- providing the input signal to a second data path of the flip-flop circuit, wherein the second data path provides a second path inverted value of the input signal to the output node via a master latch circuit and a slave latch circuit, based on a clock signal.
1 more element
An apparatus, comprising:
- a clock generation circuit configured to generate a clock signal and a clock pulse;
- a flip-flop circuit comprising:
- a first data path comprising a first inverter circuit configured to provide a first path inverted value of an input signal to an output node of the flip-flop circuit based on the clock pulse;
- and
- a second data path configured to provide a second path inverted value of the input signal to the output node via a master latch circuit, a slave latch circuit and a second inverter circuit, based on the clock signal and based on the clock pulse.
2 more elements
Dependencies are inferred from the claim text.