Circuit component sharing protocol

An electronic device, comprising:

• a first switch having a terminal;
• a second switch having first and second terminals;
• a first capacitor having a terminal coupled to the terminal of the first switch and to the first terminal of the second switch;
• a third switch having a terminal;
• a fourth switch having first and second terminals;
• a second capacitor having a terminal coupled to the terminal of the third switch and to the first terminal of the fourth switch;
• an electronic component coupled to the second terminals of the second and fourth switches;
• a first clock generator coupled to control terminals of the first and third switches, the first clock generator configured to provide first and second clock signals to control the first and third switches;
• and
• a second clock generator coupled to control terminals of the second and fourth switches and to the first clock generator, the second clock generator configured to generate third and fourth clock signals to close the second and fourth switches at mutually exclusive times.

A device, comprising:

• first output clock generator circuitry having a clock input and a clock output;
• second output clock generator circuitry having a clock input and a clock output;
• and
• third output clock generator circuitry including;
• a first flip-flop having a first data output and a first clock input;
• a second flip flop having a second data output, and a second clock input coupled to the clock output of the first output clock generator circuitry;
• a third flip-flop having a third data output, a third clock input coupled to the clock output of the second clock generator circuitry;
• a multiplexer having an output, first and second inputs, and a select input, the first input of the multiplexer coupled to the second data output of the second flip-flop, the second input of the multiplexer coupled to the third data output of the third flip-flop;
• a logic gate having an output and first and second inputs, the first input of the logic gate coupled to the first data output of the first flip-flop, the second input of the logic gate coupled to the output of the multiplexer, and the output of the logic gate coupled to the clock inputs of the first and second output clock generator circuitry;
• and
• a delay circuit having an output and an input, the output of the delay circuit coupled to the first reset input, and the input of the delay circuit coupled to the output of the logic gate.