Switched capacitor converter

An apparatus comprising:

• a clock generation circuit, the clock generation circuit comprising:
• an adaptive delay circuit to generate a first clock signal and a first clock delay signal based on a regulation clock signal;
• and
• a fixed time delay circuit to generate a second clock signal and a second clock delay signal based on the regulation clock signal;
• and
• a power train (PTR) circuit coupled to the clock generation circuit, the PTR circuit to:
• receive the first clock signal, the second clock signal, the first clock delay signal, and the second clock delay signal;
• and
• generate a voltage output signal based on the first clock signal, the second clock signal, the first clock delay signal, and the second clock delay signal.

A process of making a converter circuit, comprising:

• coupling a clock generation circuit to a power train (PTR) circuit, wherein the clock generation circuit is capable of generating a first clock signal, a second clock signal, a first clock delay signal, and a second clock delay signal;
• coupling the second clock signal and the second clock delay signal to a first PTR stage circuit of the PTR circuit;
• coupling the first clock signal and the first clock delay signal to a second PTR stage circuit of the PTR circuit;
• coupling an output of the first PTR stage circuit to an input of the second PTR stage circuit;
• and
• coupling an output of the second PTR stage circuit and the second clock signal to inputs of a third PTR stage circuit of the PTR circuit.