Globally irregular power grid

A system, comprising:

• a data processing apparatus;
• and
• a computer storage medium encoded with a computer program, the program comprising instructions that when executed by data processing apparatus cause the data processing apparatus to perform operations comprising:
• partitioning an integrated circuit design into a plurality of tiles, wherein:
• for each tile that includes within its boundaries a power switch:
• determining a width of the tile as a width of the power switch plus a first distance between adjacent power switches in a first direction,
• determining a height of the tile as a height of the power switch plus a second distance between adjacent power switches in a second direction perpendicular to the first direction, and
• centering the tile on the power switch;
• for each tile that does not include within its boundaries a power switch:
• determining a width of the tile in the first direction as half the width of the power switch plus the first distance,
• determining a height of the tile in the second direction as the height of the power switch plus the second distance, and
• placing the tile between a boundary of the integrated circuit and a tile which includes a power switch nearest the boundary of the integrated circuit;
• assigning a uniform power grid for each tile;
• for each tile, iteratively:
• determining a power parameter of a power grid within the tile;
• determining a timing metric of circuit elements of the integrated circuit;
• adjusting the power grid within each tile based on the determined power parameter and the determined timing metric;
• and
• repeating the iterations until a cessation condition is met.

A computer storage medium encoded with a computer program, the program comprising instructions that when executed by data processing apparatus cause the data processing apparatus to perform operations comprising:

• partitioning an integrated circuit design into a plurality of tiles, wherein:
• for each tile that includes within its boundaries a power switch:
• determining a width of the tile as a width of the power switch plus a first distance between adjacent power switches in a first direction,
• determining a height of the tile as a height of the power switch plus a second distance between adjacent power switches in a second direction perpendicular to the first direction, and
• centering the tile on the power switch;
• for each tile that does not include within its boundaries a power switch:
• determining a width of the tile in the first direction as half the width of the power switch plus the first distance,
• determining a height of the tile in the second direction as the height of the power switch plus the second distance, and
• placing the tile between a boundary of the integrated circuit and a tile which includes a power switch nearest the boundary of the integrated circuit;
• assigning a uniform power grid for each tile;
• for each tile, iteratively:
• determining a power parameter of a power grid within the tile;
• determining a timing metric of circuit elements of the integrated circuit;
• adjusting the power grid within each tile based on the determined power parameter and the determined timing metric;
• and
• repeating the iterations until a cessation condition is met.