Methods of operating memory device and related apparatuses

A memory system, comprising:

• a memory controller;
• and
• a memory device coupled to the memory controller and comprising an array of memory cells and a peripheral circuit, the peripheral circuit being coupled to the array of memory cells and configured to perform the following operations:
• performing, with a first set of read voltage levels for respective read voltages corresponding to a first logical page of the array of memory cells, a read operation on the first logical page to obtain a first read result of the first logical page;
• performing, with a second set of read voltage levels for the respective read voltages corresponding to the first logical page, a read operation on the first logical page to obtain a second read result of the first logical page, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels;
• performing, with a third set of read voltage levels for the respective read voltages corresponding to the first logical page, a read operation on the first logical page to obtain a third read result of the first logical page, wherein the third set of read voltage levels has a second offset relative to the first set of read voltage levels, the second offset being different from the first offset;
• performing, with a fourth set of read voltage levels for respective read voltages corresponding to a second logical page of the array of memory cells, a read operation on the second logical page to obtain a fourth read result of the second logical page, the second logical page being different from the first logical page;
• and
• determining a set of optimal read voltage levels for the respective read voltages corresponding to the first logical page based on the first read result, the second read result, the third read result, and the fourth read result.

A memory controller configured to control a memory device, the memory controller comprising:

• a memory interface for connecting the memory controller with the memory device;
• a processor;
• and
• a memory coupled to the processor and storing instructions which, when executed by the processor, cause the processor to perform the following operations:
• instructing the memory interface to send a first read command to the memory device to perform a read operation on a first logical page of the memory device with a first set of read voltage levels for respective read voltages corresponding to the first logical page, and receive a first read result of the first logical page from the memory device;
• instructing the memory interface to send a second read command to the memory device to perform a read operation on the first logical page with a second set of read voltage levels for the respective read voltages corresponding to the first logical page, and receive a second read result of the first logical page from the memory device, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels;
• instructing the memory interface to send a third read command to the memory device to perform a read operation on the first logical page with a third set of read voltage levels for the respective read voltages corresponding to the first logical page, and receive a third read result of the first logical page from the memory device, wherein the third set of read voltage levels has a second offset relative to the first set of read voltage levels, the second offset being different from the first offset;
• instructing the memory interface to send a fourth read command to the memory device to perform a read operation on a second logical page of the memory device with a fourth set of read voltage levels for respective read voltages corresponding to the second logical page, and receive a fourth read result of the second logical page from the memory device, the second logical page being different from the first logical page;
• and
• determining a set of optimal read voltage levels for the respective read voltages corresponding to the first logical page based on the first read result, the second read result, the third read result, and the fourth read result.