Circuit and method for accurately clamping source-to-drain voltage of eprom bit-cell

A memory circuit, comprising:

• an array of memory cell transistors coupled to respective bitlines;
• bias transistors, each having a source, a drain, and a gate, the source of each bias transistor coupled to a respective one of the bitlines;
• a bias node coupled to the gates of the bias transistors;
• a current source having first and second terminals, the first terminal coupled to the bias node, and the second terminal coupled to a reference node;
• and
• clamp transistors, each having a source, a drain, and a gate, the gate and source of each clamp transistor coupled to a respective one of the bitlines, and the drain of each clamp transistor coupled to a clamp node.

A method, comprising:

• forming bias transistors on or in a semiconductor layer, the bias transistors in a first row and spaced apart from one another along a first direction and having respective gates with a first width along a second direction that is orthogonal to the first direction;
• forming clamp transistors in a parallel second row on or in the semiconductor layer, the clamp transistors spaced apart from one another along the first direction and spaced apart from respective ones of the bias transistors along the second direction and having respective gates with a second width along the second direction that is less than the first width;
• connecting a source of the bias transistors to a respective one of bitlines of a memory array;
• connecting gates of the bias transistors to a bias node;
• and
• connecting each of the clamp transistors between a clamp node and a respective one of the bitlines.