Memory device for performing erase operation and operating method of the memory device
AssigneeSK hynix Inc.
InventorsMu Sun KIM, Sung Hwa HONG, Seung Il KIM, Yong Ho KIM, Byoung Jun PARK, Joo Hyun PARK
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AssigneeSK hynix Inc.
InventorsMu Sun KIM, Sung Hwa HONG, Seung Il KIM, Yong Ho KIM, Byoung Jun PARK, Joo Hyun PARK
Estimating the term…
A memory device includes a memory block including memory cells arranged corresponding to bit lines and word lines, a peripheral circuit configured to perform an erase operation of erasing data stored in the memory cells, and an erase operation controller configured to apply an erase verify voltage to the word lines during the erase operation, and determine whether the erase operation is completed based on a result of comparing a predetermined reference count with a fail bit count, the fail bit count corresponding to a number of bit lines coupled to one or more memory cells having threshold voltages greater than the erase verify voltage, wherein the predetermined reference count is a sum of a predetermined reference value and a number of masking fail columns in which a masking operation fails among the bit lines.
A memory device comprising:
A memory device comprising:
A method of operating a memory device comprising a page buffer including an input/output latch, a transfer latch, and a sensing latch, the method comprising:
Dependencies are inferred from the claim text.