High performance static random-access memory

A system, comprising:

• an array of static random-access memory (SRAM) cells;
• and
• a control circuit to perform at least one of a write or read operation in the array, wherein:
• the array comprises a column of SRAM cells;
• the column of memory cells comprises at least first and second pairs of bit lines;
• the first pair of bit lines comprises a primary bit line and a complementary bit line coupled to respective access transistors of a first subset of cells of the column;
• and
• the second pair of bit lines comprises a primary bit line and a complementary bit line coupled to the respective access transistors of a second subset of cells of the column.

A stacked structure, comprising:

• a p-type transistor layer;
• an n-type transistor layer, wherein the p-type transistor layer is below the n-type transistor layer;
• a column of memory cells formed by transistors in the p-type transistor layer and the n-type transistor layer;
• a bottom metal layer below the p-type transistor layer;
• and
• a top metal layer above the n-type transistor layer, wherein a first set of bit lines for the column of memory cells comprise portions of the top metal layer and a second set of bit lines for the column of memory cells comprise portions of the bottom metal layer.