US 2026/0094641 A1 · STATIC RANDOM-ACCESS MEMORY WITH PER ROW WRITE-ASSIST

Abstract

Embodiments herein relate to Static Random-Access Memory (SRAM) where a write assist technique is facilitated using power supply lines (Vcc) which extend in a word line direction. The SRAM can be implemented using complementary field-effect transistor (CFET) technology, where n-type and p-type transistors are arranged in a stacked configuration on top and bottom levels, respectively of a stack. In one aspect, a power supply line is shared by a row of adjacent memory cells. In another aspect, a power supply line is shared by a row of memory cells in alternate columns. The configurations avoid disturb of unselected cells due to a Vcc collapse during writing. In another aspect, an eight-transistor SRAM memory cell includes transistor gates to reduce Vmin, the minimum supply voltage at which a memory array can operate without failure.

Claims20

Dependent claims

An apparatus, comprising:

a set of memory cells arranged in a plurality of rows and a plurality of columns, wherein the memory cells comprise p-type transistors in a p-type transistor layer and n-type transistors in an n-type transistor layer, and the p-type transistor layer and the n-type transistor layer are in a stack, one layer above the other;
word lines coupled to the set of memory cells, wherein the word lines extend in a direction of the plurality of rows;
bit lines coupled to the set of memory cells, wherein the bit lines extend in a direction of the plurality of columns;
and
one or more power supply lines coupled to the set of memory cells, wherein the one or more power supply lines extend in the direction of the plurality of rows across the plurality of columns.

2 more elements

Dependencies are inferred from the claim text.

Static random-access memory with per row write-assist

Life of this patent

Static random-access memory with per row write-assist

Life of this patent

Abstract

Claims20