Memory device and system-in-package including the same

A memory device comprising:

• a buffer die comprising a PHY interface;
• a core die comprising a memory cell array and on the buffer die;
• and
• a through-silicon via penetrating through the core die,
• the PHY interface comprising:
• a clock signal generating circuit configured to generate a plurality of phase-shifted clock signals based on a clock signal;
• a comparator configured to compare a received data signal sampled based on the phase-shifted clock signals with each of a first reference voltage and a second reference voltage and configured to output first comparison signals;
• a decoder configured to perform a duo-binary decoding on the first comparison signals;
• a delay circuit configured to delay the clock signal;
• and
• a phase detecting circuit configured to control the delay circuit,
• wherein the phase detecting circuit is further configured to generate a phase-shifted training clock signal having a phase different from the phase-shifted clock signals during a training operation,
• wherein the comparator is further configured to output second comparison signals obtained by comparing the received data signal sampled based on the phase-shifted training clock signal with each of the first reference voltage and the second reference voltage during the training operation, and
• wherein the phase detecting circuit is configured to control the delay circuit based on the first comparison signals and the second comparison signals during the training operation.

A system-in-package comprising:

• a package substrate;
• an interposer on the package substrate;
• and
• a memory device and a system-on-chip on the interposer, the memory device comprising:
• a buffer die comprising a PHY interface;
• core dies on the buffer die;
• and
• a through-silicon via penetrating through the core dies, the PHY interface comprising:
• a phase adjusting circuit configured to generate a plurality of phase-shifted clock signals and a phase-shifted training clock signal based on a clock signal received from the system-on-chip and configured to delay the clock signal based on a plurality of comparison signals output from a comparator;
• the comparator configured to compare training data received from a memory controller with each of a first reference voltage and a second reference voltage based on the phase-shifted clock signals and the phase-shifted training clock signal to output the plurality of comparison signals;
• and
• a decoder configured to perform a duo-binary decoding on the comparison signals based on the phase-shifted clock signals.