Memory using ferroelectric or antiferroelectric capacitors and diodes in stacked configurations

An integrated circuit (IC) die, comprising:

• a device layer comprising a plurality of transistors;
• a memory array comprising a plurality of memory cells, each memory cell comprising:
• a first diode in a first layer comprising a first insulator material between a first electrode and a shared electrode, the first diode further comprising a first interfacial layer contacting the shared electrode;
• a second diode in the first layer comprising a second insulator material between a second electrode and the shared electrode, the second diode further comprising a second interfacial layer contacting the second electrode;
• and
• a capacitor comprising a ferroelectric or an antiferroelectric material in a second layer;
• and
• wherein the device layer is between the first layer and the second layer and a surface of the IC die.

A system comprising:

• an integrated circuit (IC) die, comprising:
• memory circuitry comprising a plurality of memory cells, each memory cell comprising first and second diodes, and a capacitor, the capacitor comprising a ferroelectric (FE) or an antiferroelectric (AFE) material;
• a device layer comprising a plurality of transistors;
• a memory layer comprising the memory circuitry, wherein the device layer is between the memory layer and a surface of the IC die;
• and
• a power supply coupled to the IC die to power the IC die.