US 2026/0094634 A1 · PREDECODERS WITH WRITE LOGIC BYPASS PATH AND MEMORY STRUCTURE INCLUDING PREDECODERS

Abstract

Disclosed are predecoders and structures including the predecoders. Each predecoder includes, among other components, first and second latches controlled by write and read clock signals, respectively, and a multiplexer-enabled write logic bypass path. During a write, an address signal is latched by the first latch and propagated through logic downstream of the first latch (including through a write logic block) to the second latch (which is transparent). During a read, the write logic bypass path is activated so the address signal bypasses the first latch and the write logic block and is instead propagated only through logic downstream of the write logic block to the second latch (which periodically latches the received signal). In both operations, a predecoded address signal is output but, due to activation of the write logic bypass path during the read, the time between receiving the address signal and outputting the predecoded address signal is reduced.

Claims20

Dependent claims

A structure comprising:

a multiplexer including:
an input terminal connected to a first signal node;
an additional input terminal;
and an output terminal;
a first latch controlled by a first clock signal;
a write logic block, wherein the first latch and the write logic block are connected between the first signal node and the additional input terminal;
a predecode logic block;
and
a second latch controlled by a second clock signal different from the first clock signal, wherein the predecode logic block and the second latch are connected between the output terminal and a second signal node.

6 more elements

A structure comprising:

a first multiplexer having a first input terminal connected to a first signal node;
an additional first input terminal;
and a first output terminal;
a first latch controlled by a first clock signal;
a write logic block, wherein the first latch and the write logic block are connected between the first signal node and the additional first input terminal;
a second multiplexer having a second input terminal;
an additional second input terminal;
and a second output terminal;
a redundancy logic block connected between the first output terminal and the second input terminal;
a predecode logic block connected between the first output terminal and the additional second input terminal;
and
a second latch controlled by a second clock signal different from the first clock signal, wherein the second latch is connected between the second output terminal and a second signal node.

9 more elements

A structure comprising:

an address decoder for a memory bank;
and
an address predecoder connected to the address decoder and including:
a multiplexer including:
an input terminal connected to a first signal node;
an additional input terminal;
and an output terminal;
a first latch controlled by a first clock signal;
a write logic block, wherein the first latch and the write logic block are connected between the first signal node and the additional input terminal;
a predecode logic block;
and
a second latch controlled by a second clock signal different from the first clock signal, wherein the predecode logic block and the second latch are connected between the output terminal and a second signal node.

9 more elements

Dependencies are inferred from the claim text.

Predecoders with write logic bypass path and memory structure including predecoders

Life of this patent

Predecoders with write logic bypass path and memory structure including predecoders

Life of this patent

Abstract

Claims20