Assembly of Multi-Stack Memory

Abstract

An integrated circuit includes a host die and a base die, both of which are disposed on an interposer. The host die includes multiple processors, and the base die includes at least two high-bandwidth memory (HBM) stacks that are disposed on the base die and communicate with the host die through the base die and the interposer. The at least two HBM stacks and the host die are arranged in a row with the host die at one end of the row. The base die further includes a controller circuit operative to multiplex outgoing data from the at least two HBM stacks to the host die, and demultiplex incoming data from the host die to the at least two HBM stacks.

Dependencies are inferred from the claim text.