Memory device, fabrication method thereof and system

A method of fabricating a memory device, comprising:

• forming a first semiconductor structure that comprises a memory cell array comprising a plurality of word lines extending in a first direction, wherein each of the word lines is connected to a word line connection structure at its middle location;
• forming a second semiconductor structure that comprises a plurality of first control circuits and at least part of a peripheral circuit distributed in gaps between the first control circuits, wherein the first semiconductor structure and the second semiconductor structure are stacked and connected, the first control circuit comprises a first sub-control circuit disposed in a first region and connected with the word line connection structure and a second sub-control circuit disposed in a second region and a third region, wherein the second region and the third region are located at both sides of the first region in the first direction;
• forming a first interconnection layer on a side of the second semiconductor structure away from the first semiconductor structure;
• and
• forming a plurality of connection structures extending in a second direction in the second semiconductor structure, wherein one end of the connection structure is connected with the at least part of the peripheral circuit in the gaps and another end of the connection structure connected with the first interconnection layer, and wherein the second direction is perpendicular to the first direction.

A memory system, comprising:

• a memory device, comprising:
• a first semiconductor structure comprising a memory cell array, wherein the memory cell array comprises a plurality of word lines extending in a first direction with each of the word lines connected to a word line connection structure at its middle location;
• a second semiconductor structure comprising a plurality of first control circuits and at least part of a peripheral circuit distributed in gaps between the plurality of first control circuits, wherein the first semiconductor structure and the second semiconductor structure are stacked and connected, and the first control circuit comprises a first sub-control circuit disposed in a first region and connected with the word line connection structure and a second sub-control circuit disposed in a second region and a third region, wherein the second region and the third region are located at both sides of the first region in the first direction;
• a first interconnection layer located on a side of the second semiconductor structure away from the first semiconductor structure;
• and
• a plurality of connection structures, wherein each of the plurality of connection structures extends in a second direction in the second semiconductor structure and has one end connected with the at least part of the peripheral circuit in the gaps and another end connected with the first interconnection layer, and wherein the second direction is perpendicular to the first direction.