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US 2026/0094575 A1Published application
Gate driver, display device including the gate driver, and electronic device including the display device
AssigneeSamsung Display Co., Ltd.
InventorsJI-SUN KIM, KYUNGHOON CHUNG, SUNHWA LEE
Life of this patent
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Abstract
A gate driver includes a plurality of stages. Each of the stages includes first to seventh transistors. The each of the stages outputs a compensation gate signal and a data write gate signal in response to an input signal, a clock signal and a gate clock signal.
Claims20
A gate driver including a plurality of stages, wherein each of the stages comprises:
- a first transistor including a gate electrode which receives a clock signal, a first electrode which receives an input signal, and a second electrode connected to a control node;
- a second transistor including a gate electrode connected to the control node, a first electrode which receives a second low gate voltage, and a second electrode connected to an inversion control node;
- a third transistor including a gate electrode connected to the control node, a first electrode which receives a high gate voltage, and a second electrode connected to the inversion control node;
- a fourth transistor including a gate electrode connected to the control node, a first electrode which receives the second low gate voltage, and a second electrode connected to a compensation gate output node from which a compensation gate signal is output;
- a fifth transistor including a gate electrode connected to the inversion control node, a first electrode which receives the high gate voltage, and a second electrode connected to the compensation gate output node;
- a sixth transistor including a gate electrode connected to the compensation gate output node, a first electrode which receives the high gate voltage, and a second electrode connected to a data write gate output node from which a data write gate signal is output;
- and
- a seventh transistor including a gate electrode connected to the inversion control node, a first electrode which receives a gate clock signal, and a second electrode connected to the data write gate output node.
5 more elements
A display device comprising:
- a display panel including a pixel;
- a data driver which provides a data voltage to the pixel;
- a gate driver which provides a gate signal to the pixel;
- an emission driver which provides an emission signal to the pixel;
- and
- a driving controller which controls the data driver, the gate driver, and the emission driver,
- wherein the gate driver comprises a plurality of stages, and
- wherein each of the stages comprises:
- a first transistor including a gate electrode which receives a clock signal, a first electrode which receives an input signal, and a second electrode connected to a control node;
- a second transistor including a gate electrode connected to the control node, a first electrode which receives a second low gate voltage, and a second electrode connected to an inversion control node;
- a third transistor including a gate electrode connected to the control node, a first electrode which receives a high gate voltage, and a second electrode connected to the inversion control node;
- a fourth transistor including a gate electrode connected to the control node, a first electrode which receives the second low gate voltage, and a second electrode connected to a compensation gate output node from which a compensation gate signal is output;
- a fifth transistor including a gate electrode connected to the inversion control node, a first electrode which receives the high gate voltage, and a second electrode connected to the compensation gate output node;
- a sixth transistor including a gate electrode connected to the compensation gate output node, a first electrode which receives the high gate voltage, and a second electrode connected to a data write gate output node from which a data write gate signal is output;
- and
- a seventh transistor including a gate electrode connected to the inversion control node, a first electrode which receives a gate clock signal, and a second electrode connected to the data write gate output node.
13 more elements
An electronic device comprising:
- a display panel including a pixel;
- a data driver which provides a data voltage to the pixel;
- a gate driver which provides a gate signal to the pixel;
- an emission driver which provides an emission signal to the pixel;
- a driving controller which controls the data driver, the gate driver, and the emission driver;
- and
- a processor which controls the driving controller,
- wherein the gate driver comprises a plurality of stages, and
- wherein each of the stages comprises:
- a first transistor including a gate electrode which receives a clock signal, a first electrode which receives an input signal, and a second electrode connected to a control node;
- a second transistor including a gate electrode connected to the control node, a first electrode which receives a second low gate voltage, and a second electrode connected to an inversion control node;
- a third transistor including a gate electrode connected to the control node, a first electrode which receives a high gate voltage, and a second electrode connected to the inversion control node;
- a fourth transistor including a gate electrode connected to the control node, a first electrode which receives the second low gate voltage, and a second electrode connected to a compensation gate output node from which a compensation gate signal is output;
- a fifth transistor including a gate electrode connected to the inversion control node, a first electrode which receives the high gate voltage, and a second electrode connected to the compensation gate output node;
- a sixth transistor including a gate electrode connected to the compensation gate output node, a first electrode which receives the high gate voltage, and a second electrode connected to a data write gate output node from which a data write gate signal is output;
- and
- a seventh transistor including a gate electrode connected to the inversion control node, a first electrode which receives a gate clock signal, and a second electrode connected to the data write gate output node.
14 more elements
Dependencies are inferred from the claim text.