Memory circuits and methods for encoder/decoder dual mode for compute-in-memory

An integrated circuit, comprising:

• a plurality of compute-in-memory (CIM) circuits, each of the plurality of CIM circuits configured to output a respective plurality of multiply-accumulate (MAC) results;
• wherein each of the plurality of CIM circuits at least comprises:
• a data multiplexer configured to:
• forward a plurality of first data elements through a first data path, in response to receiving an enable signal configured with a first logic state;
• or
• forward the plurality of first data elements through a second data path, in response to receiving the enable signal configured with a second logic state;
• and
• a plurality of computing cells configured to:
• receive a plurality of second data elements;
• and
• output the respective MAC results based on the plurality of second data elements received and the plurality of first data elements forwarded by the data multiplexer.

A method, comprising:

• receiving a plurality of first data elements, a plurality of second data elements, and an enable signal;
• selecting, in response to identifying that the enable signal is equal to a first logic state, a first data path to forward the plurality of first data elements received through an input circuit and a memory array to a plurality of computing cells, wherein the plurality of computing cells are configured to perform multiply-accumulate (MAC) operations on the plurality of first data elements and a plurality of second data elements;
• and
• selecting, in response to identifying that the enable signal is equal to a second logic state, a second data path to forward the plurality of first data element received through the input circuit to the plurality of computing cells.