Multi-stage digital perceptron architecture

A modular perceptron, comprising:

• a first n-input wide multiplexor operable to receive an n-input wide numeric vector having multiple input values and operable to select a particular input value of the multiple input values of the n-input wide numeric vector;
• a second n-input wide multiplexor operable to receive an n-input wide weight vector having multiple weight input values and operable to select a particular weight value of the multiple weight input values of the n-input wide weight vector;
• a first register operable to receive the particular numerical value from the first n-input wide multiplexor;
• a second register operable to receive the particular weight value from the second n-input wide multiplexor;
• a numerical and weight multiplier operable to perform a multiplication operation on the particular numerical value and the particular weight value to generate a product signal;
• a first multiplexor operable to receive the product and select between the product signal and zero as a first output;
• a counter operable to iterate on a scale of 1 from 0 to n−1 to generate a counter value;
• a second multiplexor operable to select between the counter value and zero as a second output;
• a counter logic circuitry configured to receive a global reset, to send the counter value to the first multiplexor to cause the first n-input wide multiplexor to select the particular input value;
• to send the counter value to the second multiplexor to cause the second n-input wide multiplexor to select the particular weight value, to selectively send a first reset value to the first multiplexor;
• to selectively send a second reset value to the second multiplexor;
• and to send the counter value to the counter to cause the counter to iterate;
• a product and linear combination adder operable to generate a sum output based on the first output of the first multiplexor and a third output of a third multiplexor;
• a third register operable to store the sum output of the product and linear combination adder and generate a sum output signal;
• the third multiplexor operable to receive the sum output signal from the third register, to select between the sum output signal and zero as a selected value, and to send the selected value to the product and linear combination adder as the third output;
• a non-linear activation function circuitry coupled to the third register and operable to receive the sum output signal and to generate an activation output;
• a fourth register operable to receive the activation output from the non-linear activation function circuitry and generate a perceptron output;
• a base clock circuitry configured to generate a base clock signal having a first frequency, the base clock signal being provided to the fourth register;
• and
• a sub clock circuitry configured to generate a sub clock signal having a second frequency within a range from n-times higher than the first frequency to an upper value based on a critical propagation delay between an input of the numerical and weight multiplier to the sum output of the product and linear combination adder, the sub clock signal being provided to the first register, the second register, and the third register.