Systems and methods for generating text and code to facilitate circuit design, development, and verification

A non-transitory, processor-readable medium storing instructions that, when executed by a processor, cause the processor to:

• receive text data that specifies a design parameter for a first integrated circuit;
• provide the text data as input to a first machine learning model to produce specification data having a predefined format;
• provide the specification data as input to a second machine learning model to produce first executable code that represents the specification data;
• provide the first executable code as input to a third machine learning model to (1) identify anomalous code in the first executable code and (2) remove the anomalous code from the first executable code to produce first modified executable code;
• provide the specification data as input to a fourth machine learning model to produce testbench data;
• execute a simulation based on the first modified executable code and the testbench data to produce result data;
• provide the result data as input to a fifth machine learning model to produce metric data;
• retrain the third machine learning model based on the metric data to produce a retrained third machine learning model;
• provide second executable code as input to the retrained third machine learning model to produce second modified executable code, the second executable code being different than the first executable code;
• and
• send the second modified executable code for use in producing at least a portion of a second integrated circuit.

A method, comprising:

• producing baseline signal data, via a processor, by parsing at least one of waveform data, specification data, or design data, associated with an integrated circuit;
• simulating, via the processor, register-transfer level (RTL) code associated with the design data, to produce test signal data that encodes a plurality of cycle-indexed samples associated with execution of the integrated circuit;
• executing, via the processor, the RTL code to identify a test failure and a time window associated with the test failure;
• performing, via the processor, temporal correlation analysis between the baseline signal data and the test signal data, based on the time window, to identify a propagation path that represents a root cause of the test failure and that crosses a plurality of design hierarchies associated with the plurality of cycle-indexed samples;
• and
• generating, via the processor and based on the propagation path, an RTL code patch that excludes anomalous code associated with the test failure.