Hardware Mitigation of Cache Side-Channel Attacks

Abstract

Systems and techniques for hardware mitigation of cache side-channel attacks are described. In one example, a processor includes a cache system having a shared cache level of a hierarchy of cache levels and cache controller circuitry associated with the shared cache level. The cache controller circuitry monitors access requests of each application or thread accessing the shared cache level. In response to detecting a suspicious access pattern indicative of a cache side-channel attack by a particular application, the cache controller circuitry penalizes subsequent access requests by the application. The described techniques increase the noise and complexity of cache side-channel attacks without penalizing the latency of access requests of potential victims and other applications accessing a shared cache level.

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