Oscillatory vector matrix multiplication for analog in-memory compute (aimc)

A method for controlling an oscillatory matrix-vector multiplication device, the method comprising:

• mapping a given weight to a duty cycle of a programmable oscillator circuit;
• configuring the programmable oscillator circuit to produce an oscillating signal with the mapped duty cycle;
• and
• applying the oscillating signal to a tunable resistive circuit.

An oscillatory matrix-vector multiplication device comprising:

• an array of a plurality of oscillatory matrix-vector multiplication circuits, the array 448 configured as a plurality of columns and a plurality of rows of the oscillatory matrix-vector multiplication circuits, each oscillatory matrix-vector multiplication circuit comprising:
• a first tunable resistive circuit comprising a first complementary metal-oxide semiconductor (CMOS) transistor, a first activation input, and a first tunable resistive circuit output, wherein the first complementary metal-oxide semiconductor (CMOS) transistor comprises a first gate input, a first input coupled to the first activation input and a first output coupled to the first tunable resistive circuit output;
• a second tunable resistive circuit comprising a second complementary metal-oxide semiconductor (CMOS) transistor, a second activation input, and a second tunable resistive circuit output, wherein the second complementary metal-oxide semiconductor (CMOS) transistor comprises a second gate input, a second input coupled to the second activation input and a second output coupled to the second tunable resistive circuit output;
• a programmable oscillator circuit coupled to the first gate input of the first tunable resistive circuit and coupled to the second gate input of the second tunable resistive circuit and wherein the programmable oscillator circuit is configured to produce a control signal based on a given conductance;
• and
• a plurality of summation circuits, wherein the first input of each first tunable resistive circuit in a given row of the array and the second input of each second tunable resistive circuit in the given row of the array are coupled to an activation signal corresponding to the row, wherein the first tunable resistive circuit output of each first tunable resistive circuit in a given column of the array are coupled together and the second tunable resistive circuit output of each second tunable resistive circuit in the given column of the array are coupled together and wherein one of the plurality of summation circuits is configured to subtract a current on the coupled second tunable resistive circuit outputs of the second tunable resistive circuits in the given column of the array from the coupled first tunable resistive circuit outputs of the first tunable resistive circuits in the given column of the array.

A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a semiconductor structure, wherein the HDL design structure comprises:

• one or more oscillatory matrix-vector multiplication circuits, each oscillatory matrix-vector multiplication circuit comprising:
• a first tunable resistive circuit comprising a first complementary metal-oxide semiconductor (CMOS) transistor, a first activation input, and a first tunable resistive circuit output, wherein the first complementary metal-oxide semiconductor (CMOS) transistor comprises a first gate input, a first input coupled to the first activation input and a first output coupled to the first tunable resistive circuit output, and wherein the first activation input is configured to receive an activation signal;
• and
• a programmable oscillator circuit coupled to the first gate input of the first tunable resistive circuit and configured to produce a control signal based on a given conductance.