Apparatuses and methods for managing memory access
AssigneeMicron Technology, Inc.
InventorLeon Zlotnik
Life of this patent
Estimating the term…
Abstract
Various memory access management schemes are described. Access requests received from multiple processing units in a particular order can be responded to by either providing the instructions requested by the access requests or by providing alternative instructions (or any combination thereof) that cause the processing units to re-access at a later point. The alternative instructions can be provided when the timing requirements associated with the access requests are not expected to be met, ensuring a continuous flow of access requests, which may be disrupted if the timing requirements are eventually met.
Claims20
A method, comprising:
- sequentially receiving, respectively from a plurality of processing units, a number of access requests respectively including a number of addresses of a memory to access a number of first instructions from the number of addresses;
- retrieving the number of first instructions from locations of the memory corresponding to the number of addresses;
- and
- providing, to one or more respective processing units of the plurality in an order in which the number of access requests were received, the number of first instructions or a number of second instructions instead of the number of first instructions, or any combination thereof, based on a determination of whether a respective timing requirement associated with each one of the number of first instructions is expected to be met;
- wherein each second instruction, when executed by the respective processing unit, causes the respective processing unit to access a respective address of the number of addresses.
An apparatus, comprising:
- a controller, the controller comprising a plurality of caches;
- wherein the controller is further configured to:
- receive, respectively from a plurality of processing units and in a particular order, a number of addresses corresponding to respective locations of a memory shared by the plurality of processing units;
- fetch a number of first instructions from the respective locations of the memory;
- and
- provide, at each position of the particular order and to one or more respective processing units, a respective first instruction of the number of first instructions, or a respective second instruction of a number of second instructions based on a determination of whether a timing requirement of each processing unit is expected to be met.
A system, comprising:
- a plurality of processing units;
- a memory shared by the plurality of processing units and configured to store instructions;
- and
- a controller configured to:
- sequentially receive a number of addresses respectively from the plurality of processing units, each address corresponding to a respective instruction of a number of instructions;
- fetch the number of instructions from the memory;
- to respond to each processing unit of the plurality in an order in which the number of addresses were received at the controller from the plurality of processing units:
- provide, to a respective processing unit, a respective instruction of the number of instructions in response to a determination that a timing requirement associated with provision of the respective instruction is expected to be met;
- and
- provide, to the respective processing unit, a respective alternative instruction in replacement of the respective instruction in response to a determination that a timing requirement associated with the respective instruction is not expected to be met, wherein the respective alternative instruction, when executed by the respective processing unit, causes the respective processing unit to access an address corresponding to the respective instruction.
Dependencies are inferred from the claim text.