Memory controller with oversampling memory i/o

A memory controller in an integrated circuit system, comprising:

• a transmitter module to send outgoing data to a memory module in the integrated circuit system;
• and
• a receiver module including a plurality of receiver circuits to receive incoming data modulated with pulse amplitude modulation (PAM) having N signal levels from the memory module over a plurality of data lanes, N being an integer greater than 2, each receiver circuit including:
• a plurality of (K) samplers that sample a data signal received on a data lane at a sequence of time points in a unit time interval to generate K samples, K being an in-phase oversampling factor;
• a plurality of (K) signal level detectors to receive the K samples, respectively, wherein each signal level detector includes a plurality of (R) voltage comparator blocks and R is a quadrature-phase oversampling factor, and wherein the R voltage comparator blocks are operative to compare a same one of the K samples against (N-1) voltage thresholds with different offsets configured for different voltage comparator blocks to thereby generate R signal level estimates;
• and
• a decision circuit that identifies one of the N signal levels to which the data signal is mapped based on all signal level estimates generated from the K samples, and outputs a symbol corresponding to the identified signal level.