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US 2026/0093579 A1Published application
Error correction code (ecc) initialization engine for memories
AssigneeQUALCOMM Incorporated
InventorsPrashant SINGH, Deepak BARANWAL, Gurudeep BHAT, Rohit MEHANDIRATTA
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Abstract
Aspects of the present disclosure relate to error correction code (ECC) initialization of a memory of a safety domain in a system-on-a-chip (SoC). For example, the memory of the safety domain may be segmented into multiple memory banks. The multiple memory banks are associated with multiple ECC initialization engines. The multiple ECC initialization engines are simultaneously executed to perform concurrent ECC initialization of the multiple memory banks.
Claims20
A method, comprising:
- segmenting a memory of a safety domain in a system-on-a-chip (SoC) into a plurality of memory banks, wherein the plurality of memory banks are associated with a plurality of error correction code (ECC) initialization engines;
- and
- simultaneously executing the plurality of ECC initialization engines to perform concurrent ECC initialization of one or more portions of the plurality of memory banks.
An apparatus, comprising:
- a safety domain with a memory;
- and
- one or more processors coupled to the safety domain and configured to:
- segment the memory of the safety domain into a plurality of memory banks, wherein the plurality of memory banks are associated with a plurality of error correction code (ECC) initialization engines;
- and
- simultaneously execute the plurality of ECC initialization engines to perform concurrent ECC initialization of one or more portions of the plurality of memory banks.
3 more elements
An apparatus, comprising:
- means for segmenting a memory of a safety domain in a system-on-a-chip (SoC) into a plurality of memory banks, wherein the plurality of memory banks are associated with a plurality of error correction code (ECC) initialization engines;
- and
- means for simultaneously executing the plurality of ECC initialization engines to perform concurrent ECC initialization of one or more portions of the plurality of memory banks.
Dependencies are inferred from the claim text.