US 2026/0093578 A1Published application

Data processing

AssigneeArm Limited

InventorsDaren Croxford, Jussi Tuomas Pennala, Philip Malcolm Done, Mark Stephen Bellamy

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Abstract

Disclosed is memory access logic that is operable to perform different accesses to a particular memory element depending on whether or not a memory error checking scheme is being implemented for the memory element. A set of error checking bits are stored in the memory element for implementing the memory error checking scheme. The memory error checking scheme can thus be selectively enabled and memory accesses performed accordingly such that when the memory error checking scheme is enabled, it is ensured that the required error checking bits are accessed.

Claims20

Dependent claims

An apparatus comprising:

a memory element, wherein the memory element comprises an access lane, wherein the access lane has a certain data width and is operable and configured to store within that data width a respective set of data bits and to also store within that data width an associated set of one or more error checking bits that are usable to implement a memory error checking scheme for the set of data bits, the error checking bits thus being stored in the access lane of the memory element together with the set of data bits for which the error checking bits are implementing the memory error checking scheme, and wherein the access lane is configured as a set of plural channels, each channel corresponding to a respective sub-portion of the access lane;
and
an associated memory interface circuit including memory access logic for controlling access to the respective memory element,
wherein, when new data is to be written to a sub-portion of the access lane, the memory access logic is selectively controllable to perform different memory access operations, including:
i. a first access operation comprising reading the full data width of the access lane, thus including reading all of the data bits and the corresponding error checking bits, and then writing the new data into the full data width of the access lane together with an updated set of error checking bits based on the new data;
and
ii. a second, different access operation in which the new data can be written to a selected one or more of the channels of the set of plural channels into which the access lane is configured.

4 more elements

A data processing system comprising:

at least one processing element;
a respective memory element that the at least one processing element is operable to access when performing its processing, wherein the memory element comprises an access lane, wherein the access lane has a certain data width and is operable and configured to store within that data width a respective set of data bits and to also store within that data width an associated set of one or more error checking bits that are usable to implement a memory error checking scheme for the set of data bits, the error checking bits thus being stored in the access lane together with the set of data bits for which the error checking bits are implementing the memory error checking scheme, and wherein the access lane is configured as a set of plural channels, each channel corresponding to a respective sub-portion of the access lane;
and
an associated memory interface circuit including memory access logic for controlling the at least one processing element's access to the respective memory element,
wherein the memory error checking scheme can be selectively enabled in respect of the memory element, and
wherein, when new data is to be written to a sub-portion of the access lane, the memory access logic is configured to perform different memory access operations depending on whether or not the memory error checking scheme is enabled, wherein:
when the memory error checking scheme is enabled, the memory access logic is configured to perform a first access operation comprising reading the full data width of the access lane, thus including reading all of the data bits and the corresponding error checking bits, and then writing the new data into the full data width of the access lane together with an updated set of error checking bits based on the new data,
whereas when the memory error checking scheme is not enabled, the memory access logic is operable to perform a second, different access operation in which the new data can be written to a selected one or more of the channels of the set of plural channels into which the access lane is configured.

5 more elements

A method of initialising a memory element access lane for subsequent memory accesses, wherein the memory element access lane has a certain data width and is operable and configured to store within that data width a respective set of data bits and to also store within that data width an associated set of one or more error checking bits that are usable to implement a memory error checking scheme for the set of data bits, the error checking bits thus being stored in the memory element access lane together with the set of data bits for which the error checking bits are implementing the memory error checking scheme,

wherein the memory error checking scheme can be selectively enabled in respect of the memory element, and wherein the method comprises:
when the memory error checking scheme is not enabled in respect of the memory element:
setting the value of each of the error checking bits in the set of error checking bits to a same value, the same value being whichever of 0 or 1 it is more efficient to read from the memory element access lane.

Dependencies are inferred from the claim text.

Facts

Application: 18/899,342Filed 27 Sep 2024
Published: 2 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 11/1044
In individual solid state devices: with specific ECC/EDC distribution
G06F 11/1048
In individual solid state devices: using arrangements adapted for a specific error detection or correction feature
G06F 12/023
User address space allocation, e.g. contiguous or non contiguous base addressing: free address space management
G06F 13/1668
For access to memory bus: details of memory controller

Family

US 12,670,063 B2Related patent
US 2026/0093578 A1This patent

From the US filing history. Foreign family members aren’t listed.

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