Controller and memory system

A memory system comprising:

• a plurality of memories;
• and
• a controller configured to
• perform a data read operation on remaining memories excluding an error memory, among the plurality of memories,
• perform a test read operation on the error memory, and
• sequentially perform detect read operations on memories other than one memory selected in rotation among the plurality of memories when a number of errors detected in the test read operation is smaller than a preset number.

A controller comprising:

• a control circuit configured to perform a first read operation on a plurality of memories;
• and
• an error correction circuit configured to correct an error which occurs in the first read operation,
• wherein the control circuit is configured to:
• sequentially perform second read operations on memories excluding at least one memory selected in rotation among the plurality of memories when an uncorrectable error occurs in the first read operation, and
• set, as an error memory, a memory which is excluded in a second read operation in which a smallest number of errors is corrected, among the second read operations.