Out-of-order fetch and decode pipelines

A system comprising:

• a memory;
• and
• a processor comprising:
• a plurality of fetch pipelines each configured to fetch instructions, at least one of the plurality of fetch pipelines comprising:
• a fetch queue configured to store an assigned group of instructions;
• a common operation cache configured to store predecoded operations;
• a decode circuit configured to decode instructions not found in the operation cache;
• and
• an instruction cache configured to store instructions to be decoded by the decode circuit;
• a control circuit configured to assign the assigned groups of instructions to the plurality of fetch pipelines independent from program order;
• and
• a dispatch circuit configured to receive groups of decoded operations, corresponding to the assigned groups of instructions, from the plurality of fetch pipelines via a multiplexer, coupled to each of the plurality of fetch pipelines, in program order;
• wherein the multiplexer couples each of the plurality of fetch pipelines to the dispatch circuit and is configured to receive a control signal from the control circuit for selecting between the plurality of fetch pipelines based on the program order, and
• wherein at least two of the plurality of fetch pipelines share the common operation cache.

A method comprising:

• selecting, from a plurality of fetch pipelines, a fetch pipeline of the plurality of fetch pipelines for assigning a group of instructions independently from a program order;
• fetching, for the assigned group of instructions, predecoded operations available in an common operation cache in the selected fetch pipeline, wherein at least two of the plurality of fetch pipelines share the common operation cache;
• decoding, for the assigned group of instructions upon an operation cache miss, instructions into decoded operations;
• holding the predecoded operations and the decoded operations in an operation queue of the selected fetch pipeline;
• selecting, using a multiplexer coupled to operation queues of the plurality of fetch pipelines, based on the program order;
• and
• providing, via the multiplexer, operations from the respective operation queues of each of the plurality of fetch pipelines to a dispatch circuit in the program order.