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US 2026/0093490 A1Published application
Increasing data-dependent memory prefetcher accuracy using memory metadata
AssigneeIntel Corporation
InventorsMichael LeMay, David M. Durham
Life of this patent
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Abstract
Data-dependent (memory) prefetcher support is described. In some examples, the data-dependent (memory) prefetcher utilizes metadata to predict if a data word is a valid pointer before doing a prefetch. Data words that are not deemed to be valid pointers are not used to prefetch. The metadata may be linear or physical depending on the example.
Claims20
An apparatus comprising:
- decoder circuitry configured to decode at least an instance of a single first instruction, the instance of the single first instruction to include one or more fields for an opcode, a destination memory location, and a source register identifier, wherein the opcode is to indicate that a pointer stored in the identified source register is to be compressed and the compressed pointer stored at the destination memory location;
- and
- execution circuitry configured to execute the decoded instance of the single first instruction to compress a pointer stored in the identified source register and store the compressed pointer stored at the destination memory location.
A non-transitory machine-readable medium storing at least one instruction which when executed by a processor is to cause the processor to perform a method, the method comprising:
- decoding at least an instance of a single first instruction, the instance of the single first instruction to include one or more fields for an opcode, a destination memory location, and a source register identifier, wherein the opcode is to indicate that a pointer stored in the identified source register is to be compressed and the compressed pointer stored at the destination memory location;
- and
- executing the decoded instance of the single first instruction to compress a pointer stored in the identified source register and store the compressed pointer stored at the destination memory location.
A system comprising:
- memory to at least store instance of a single first instruction;
- decoder circuitry configured to decode at least the instance of a single first instruction, the instance of the single first instruction to include one or more fields for an opcode, a destination memory location, and a source register identifier, wherein the opcode is to indicate that a pointer stored in the identified source register is to be compressed and the compressed pointer stored at the destination memory location;
- and
- execution circuitry configured to execute the decoded instance of the single first instruction to compress a pointer stored in the identified source register and store the compressed pointer stored at the destination memory location.
1 more element
Dependencies are inferred from the claim text.