Vector floating-point flag update with micro-operations

A computer program product embodied in a non-transitory computer readable medium for vector processing, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:

• accessing a processor core, wherein the processor core is coupled to a memory hierarchy, and wherein the processor core is configured to execute vector floating-point instructions and micro-operations;
• decoding a vector floating-point instruction, wherein the decoding includes replacing the vector floating-point instruction with one or more vector floating-point micro-operations (VFPMs);
• assigning, by a reorder buffer (ROB), a reorder buffer ID (ROBID) to each of the one or more VFPMs, wherein the assigning includes a micro-sequencer ID (MSID);
• executing, by the processor core, the one or more VFPMs, wherein the executing includes requiring, by a first VFPM within the one or more VFPMs, a first update to an architectural floating-point flag;
• and
• setting the architectural floating-point flag, wherein the setting is based on the first update, and wherein the setting occurs after the one or more VFPMs have been committed by the processor core.

A computer system for vector processing comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access a processor core, wherein the processor core is coupled to a memory hierarchy, and wherein the processor core is configured to execute vector floating-point instructions and micro-operations;
• decode a vector floating-point instruction, wherein the decoding includes replacing the vector floating-point instruction with one or more vector floating-point micro-operations (VFPMs);
• assign, by a reorder buffer (ROB), a reorder buffer ID (ROBID) to each of the one or more VFPMs, wherein the assigning includes a micro-sequencer ID (MSID);
• execute, by the processor core, the one or more VFPMs, wherein the executing includes requiring, by a first VFPM within the one or more VFPMs, a first update to an architectural floating-point flag;
• and
• set the architectural floating-point flag, wherein the setting is based on the first update, and wherein the setting occurs after the one or more VFPMs have been committed by the processor core.