Memory Controller with Dynamic Signaling Schemes

The method of claim 1, further comprising:

• receiving another indication of a decreased demand for data transfer in the second direction;
• and
• decreasing the second PAM level in the second direction independently of the target PAM level in the first direction.

The method of claim 1, wherein receiving the indication further comprises:

• receiving, from a processor coupled to the memory controller, more requests for data transfer in the first direction than in the second direction.

The method of claim 1, wherein the memory controller adjusts the PAM levels for data transmission and reception based on statuses of a write queue and a read queue, respectively, in the memory controller.

The method of claim 1, wherein the first direction is a direction of reading from the memory module, the method further comprises:

• activating additional voltage comparators when increasing the first PAM level to compare a received data voltage with voltage thresholds of the target PAM level.

The method of claim 1, wherein the first direction is a direction of writing to the memory module, the method further comprises:

• activating additional weighted current sources to convert outgoing symbols to voltage levels of the target PAM level.

The method of claim 1, wherein the memory module is one of a double data rate (DDR)-based memory module and a high bandwidth memory (HBM) module.

The method of claim 8, further comprising:

• dynamically increasing the at least one of the first PAM level and the second PAM level in response to an increase in workload of the integrated circuit system.

The method of claim 8, further comprising:

• dynamically decreasing the at least one of the first PAM level and the second PAM level in response to the change in power status of the integrated circuit system.

The method of claim 1, wherein the memory module is one of a double data rate (DDR)-based memory module and a high bandwidth memory (HBM) module.

The integrated circuit system of claim 12, wherein, when the memory controller receives another indication of a decreased demand for data transfer in the second direction, the memory controller decreases the second PAM level in the second direction independently of the target PAM level in the first direction.

The integrated circuit system of claim 12, wherein the memory controller is coupled to a processor, and wherein the indication of the increased demand is more requests from the processor for data transfer in the first direction than in the second direction.

The integrated circuit system of claim 12, wherein the memory controller adjusts the PAM levels for data transmission and reception based on statuses of a write queue and a read queue, respectively, in the memory controller.

The integrated circuit system of claim 12, wherein the first direction is a direction of reading from the memory module, and wherein the memory controller, when increasing the first PAM level, activates additional voltage comparators to compare a received data voltage with voltage thresholds of the target PAM level.

The integrated circuit system of claim 12, wherein the first direction is a direction of writing to the memory module, and wherein the memory controller, when increasing the first PAM level, activates additional weighted current sources to convert outgoing symbols to voltage levels of the target PAM level.

The integrated circuit system of claim 12, wherein, when the memory controller receives an indication of a change in operating conditions that affects performance of the integrated circuit system, the memory controller changes at least one of the first PAM level and the second PAM level in response to the change.

The integrated circuit system of claim 11, wherein the memory module is a double data rate (DDR)-based memory module.

The integrated circuit system of claim 11, wherein the memory module is a high bandwidth memory (HBM) module.