Active matrix substrate and display device

An active matrix substrate that includes a display region including a plurality of pixel regions and a non-display region located around the display region, the active matrix substrate comprising:

• a substrate;
• a plurality of wiring lines provided on the substrate, the plurality of wiring lines including a plurality of gate wiring lines and a plurality of source wiring lines;
• a plurality of TFTs supported by the substrate, the plurality of TFTs including a plurality of pixel TFTs disposed in the display region and a plurality of circuit TFTs disposed in the non-display region;
• and
• a plurality of ESD protection elements disposed in the non-display region, each of the plurality of ESD protection elements being electrically connected to a corresponding wiring line of the plurality of wiring lines,
• wherein at least some TFTs of the plurality of TFTs include
• a first oxide semiconductor layer including a first channel region, and a first source contact region and a first drain contact region located on both sides of the first channel region,
• a first gate insulating layer provided at least on the first channel region,
• a first gate electrode facing the first channel region via the first gate insulating layer, and
• a first source electrode and a first drain electrode electrically connected to the first source contact region and the first drain contact region, respectively, and
• each of the plurality of ESD protection elements includes
• a second oxide semiconductor layer including a second channel region, and a second source contact region and a second drain contact region located on both sides of the second channel region, the second oxide semiconductor layer being formed in a layer separated from the first oxide semiconductor layer and having a mobility lower than a mobility of the first oxide semiconductor layer,
• a second gate insulating layer provided at least on the second channel region,
• a second gate electrode facing the second channel region via the second gate insulating layer, and
• a second source electrode and a second drain electrode electrically connected to the second source contact region and the second drain contact region, respectively.