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US 2026/0090455 A1Published application
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorJongwan Seo
Life of this patent
Estimating the term…
Abstract
The technical idea of the inventive concept provides a semiconductor package including a first package substrate, a second package substrate on the first package substrate, a plurality of semiconductor chips on the second package substrate, a molding member on the second package substrate and configured to surround the plurality of semiconductor chips, and a gas barrier layer on the molding member.
Claims20
A semiconductor package comprising:
- a first package substrate;
- a second package substrate on the first package substrate;
- a plurality of semiconductor chips on the second package substrate;
- a molding member on the second package substrate and configured to surround the plurality of semiconductor chips;
- and
- a gas barrier layer on the molding member.
3 more elements
A semiconductor package comprising:
- a first package substrate;
- a second package substrate on the first package substrate and electrically connected to the first package substrate via substrate connection terminals;
- a substrate under-fill material layer between the second package substrate and the first package substrate and configured to surround the substrate connection terminals;
- a plurality of semiconductor chips horizontally spaced apart from each other on the second package substrate;
- a molding member on the second package substrate and configured to surround the plurality of semiconductor chips;
- a gas barrier layer comprising a first portion configured to cover an upper surface of the molding member and upper surfaces of the plurality of semiconductor chips, a second portion configured to cover a side surface of the molding member, a side surface of the second package substrate, and a side surface of the substrate under-fill material layer, and a third portion configured to cover an upper surface of the first package substrate, wherein the upper surface of the first package substrate does not vertically overlap the second package substrate;
- and
- a stiffener configured to extend in a vertical direction of the first package substrate along an edge of the first package substrate and on the third portion of the gas barrier layer.
5 more elements
A semiconductor package comprising:
- a package substrate;
- at least one semiconductor chip on the package substrate;
- a molding member on the package substrate and configured to surround the at least one semiconductor chip;
- and
- a gas barrier layer between the package substrate and the molding member and between the at least one semiconductor chip and the molding member.
2 more elements
Dependencies are inferred from the claim text.