Semiconductor device and associated method in a fan-out wafer level chip scale package
AssigneeSTMicroelectronics International N.V.
InventorLoic Pierre Louis RENARD
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AssigneeSTMicroelectronics International N.V.
InventorLoic Pierre Louis RENARD
Estimating the term…
In accordance with various embodiments of the present disclosure, a fan-out wafer-level chip scale package is provided that comprises a semiconductor die having a top side with an active layer, an opposing bottom side, and four peripheral sides; a molding compound surrounding the peripheral sides of the semiconductor die; a redistribution layer at least partially embedded in a dielectric layer and providing a plurality of electrical connections to the semiconductor die; a plurality of solder balls on the redistribution layer, each of the plurality of solder balls providing an electrical connection to a corresponding connection point of the semiconductor die; and a first conductive wall embedded in the molding compound adjacent and substantially parallel to a first one of the peripheral sides of the semiconductor die, the first conductive wall having a top edge in electrical contact with the redistribution layer.
A method of manufacturing a semiconductor device, the method comprising:
A fan-out wafer-level chip scale package (FO-WLCSP) comprising:
Dependencies are inferred from the claim text.