US 2026/0090420 A1 · PACKAGE STRUCTURE AND FORMING METHOD THEREOF

Abstract

A package structure and a forming method thereof are disclosed. In the package structure, two adjacent first chips arranged in a row direction are interconnected through a first wiring, two adjacent first chips arranged in a column direction are interconnected through a second wiring, and lengths of the first wiring and the second wiring are the same, so that two adjacent first chips can be interconnected in both the row direction and the column direction, thereby increasing connection channels and enhancing the bandwidth. In addition, since the lengths of the first wiring and the second wiring are the same, rates for various same or different communications or data transmissions between the two adjacent first chips arranged in rows and columns can remain consistent or vary slightly in the row direction and the column direction, thereby improving performance of the package structure.

Claims20

Dependent claims

A package structure, comprising:

a substrate, wherein the substrate has a plurality of discrete first wirings for interconnection in a row direction and a plurality of discrete second wirings for interconnection in a column direction, and a length of the second wiring is equal to a length of the first wiring;
a plurality of first chips, wherein the plurality of first chips are arranged in rows and columns on an upper surface of the substrate, two adjacent first chips arranged in the row direction are interconnected through the first wiring, and two adjacent first chips arranged in the column direction are interconnected through the second wiring;
and
a second chip mounted on a back surface of the first chip, wherein the second chip is electrically connected to the first chip.

1 more element

A forming method for a package structure, comprising:

providing a substrate, wherein the substrate has a plurality of discrete first wirings for interconnection in a row direction and a plurality of discrete second wirings for interconnection in a column direction, and a length of the second wiring is equal to a length of the first wiring;
providing a plurality of first chips, wherein the plurality of first chips are arranged in rows and columns on an upper surface of the substrate, two adjacent first chips arranged in the row direction are interconnected through the first wiring, and two adjacent first chips arranged in the column direction are interconnected through the second wiring;
and
mounting a second chip on a back surface of the first chip, wherein the second chip is electrically connected to the first chip.

1 more element

Dependencies are inferred from the claim text.

Package structure and forming method thereof

Life of this patent

Package structure and forming method thereof

Life of this patent

Abstract

Claims20