Semiconductor package

A semiconductor package comprising:

• a first wiring structure comprising a first wiring pattern and a first wiring insulating layer surrounding the first wiring pattern;
• a first semiconductor chip above the first wiring structure;
• a second semiconductor chip above the first wiring structure and spaced apart from the first semiconductor chip in a horizontal direction;
• a heat dissipation member above the first semiconductor chip and the second semiconductor chip;
• a molding film bonding the heat dissipation member to the first semiconductor chip and the second semiconductor chip;
• and
• a molding member on the first wiring structure and surrounding side surfaces of each of the first semiconductor chip and the second semiconductor chip,
• wherein a thermal conductivity of the molding film is greater than a thermal conductivity of the molding member.

A semiconductor package comprising:

• a first wiring structure comprising a first wire and a first wiring insulating layer surrounding the first wire;
• a first semiconductor chip above the first wiring structure and connected to the first wiring structure via a first chip connection bump;
• a second semiconductor chip above the first wiring structure and connected to the first wiring structure via a second chip connection bump, the second semiconductor chip spaced apart from the first semiconductor chip in a horizontal direction;
• a dummy block on the first wiring structure and spaced apart from each of the first semiconductor chip and the second semiconductor chip in the horizontal direction;
• an adhesive layer comprising a first portion on an upper surface of the first semiconductor chip, and further comprising a second portion on an upper surface of the second semiconductor chip;
• a molding member on the first wiring structure and surrounding side surfaces of each of the first semiconductor chip, the second semiconductor chip, the dummy block, and the adhesive layer;
• and
• a heat dissipation member on an upper surface of each of the molding member, the dummy block, and the adhesive layer,
• wherein the molding member is between the first semiconductor chip and the first wiring structure and between the second semiconductor chip and the first wiring structure, and the molding member surrounds the first chip connection bump and the second chip connection bump,
• wherein a surface of the first chip connection bump, that faces away from the first semiconductor chip, and a surface the second chip connection bump, that faces away from the second semiconductor chip, are flat, and
• wherein the upper surface of the adhesive layer is coplanar with the upper surface of the molding member.