Metal-insulator-metal device with improved performance

An integrated chip, comprising:

• a first conductive plate comprising a lower surface and a lower sidewall protruding downward from the lower surface;
• a second conductive plate disposed over the first conductive plate;
• a third conductive plate disposed over the second conductive plate;
• a dielectric structure separating the first conductive plate, the second conductive plate, and the third conductive plate from one another;
• a first conductive structure contacting sidewalls of the first conductive plate and the third conductive plate along interfaces that are vertically between bottommost and topmost surfaces of the third conductive plate;
• and
• a second conductive structure contacting a sidewall of the second conductive plate along an interface that is vertically between bottommost and topmost surfaces of the second conductive plate.

An integrated chip, comprising:

• a first titanium nitride plate disposed over a substrate;
• a first hafnium aluminum oxide layer disposed over the first titanium nitride plate;
• a second titanium nitride plate disposed over the first hafnium aluminum oxide layer;
• a second hafnium aluminum oxide layer disposed over the second titanium nitride plate;
• a third titanium nitride plate disposed over the second hafnium aluminum oxide layer, wherein an outermost sidewall of the second titanium nitride plate, which faces an interior sidewall of the third titanium nitride plate, is vertically above an upper surface of the first titanium nitride plate;
• and
• a conductive structure contacting sidewalls of the first titanium nitride plate, the second hafnium aluminum oxide layer, and the third titanium nitride plate, wherein the conductive structure contacts the sidewalls of the third titanium nitride plate and the second hafnium aluminum oxide layer above the upper surface of the first titanium nitride plate.