US 2026/0090353 A1 · BIFACIAL SEMICONDUCTOR WAFER

Abstract

A semiconductor device having one or more bifacial semiconductor wafers. The bifacial semiconductor wafer includes a first array of semiconductor dies on a first planar surface and a second array of semiconductor dies on a second planar surface that is opposite the first planar surface. The first array of semiconductor dies are electrically coupled via a first redistribution layer and the second array of semiconductor dies are electrically coupled via a second redistribution layer. One or more through silicon vias electrically couple the first array of semiconductor dies with the second array of semiconductor dies.

Claims20

Dependent claims

A semiconductor device, comprising:

a bifacial semiconductor wafer having a first planar surface and a second planar surface opposite the first planar surface;
a first plurality of semiconductor dies provided on the first planar surface;
a second plurality of semiconductor dies provided on the second planar surface;
and
a plurality of through silicon vias electrically coupling the first plurality of semiconductor dies on the first planar surface with the second plurality of semiconductor dies on the second planar surface.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/407,597Filed 3 Dec 2025

Priority

16 Aug 2022

Published

26 Mar 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 90/00
Package configurations
H10D 88/101
Three-dimensional [3D] integrated devices: comprising components on opposite major surfaces of semiconductor substrates
H10W 80/00
Direct bonding of chips, wafers or substrates

Bifacial semiconductor wafer

Life of this patent

Bifacial semiconductor wafer

Life of this patent

Abstract

Claims20