Semiconductor dies and semiconductor wafers for detecting misalignment of chip bonding pads

A semiconductor die comprising:

• a first semiconductor die comprising first bonding metal pads and a plurality of first test pad groups that each includes first test pads, wherein the first bonding metal pads are connected to a cell array structure comprising a plurality of memory blocks, and the first test pads of each of the plurality of first test pad groups are electrically connected to each other through a line extending in a first direction;
• a second semiconductor die comprising second bonding metal pads in contact with the first bonding metal pads, respectively, and a plurality of second test pad groups that each includes second test pads, wherein the second bonding metal pads are connected to a core peripheral circuit structure comprising circuits connected to the plurality of memory blocks, respectively, and wherein the plurality of second test pad groups are arranged at positions respectively corresponding to positions of the plurality of first test pad groups, and the second test pads of each of the plurality of second test pad groups are electrically connected to each other through a line extending in a third direction that transverses the first direction;
• and
• a detector configured to determine a degree of accuracy in alignment between the first semiconductor die and the second semiconductor die, based on current flowing between the first test pads of each of the plurality of first test pad groups and the second test pads of each of the plurality of second test pad groups, with the first semiconductor die and the second semiconductor die being coupled to each other.

A semiconductor wafer comprising:

• a first semiconductor wafer comprising first semiconductor dies arranged in a first direction and a third direction traversing the first direction, wherein each of the first semiconductor dies comprises a plurality of first test pad groups that each includes first test pads, and the first test pads of each of the plurality of first test pad groups are electrically connected to each other through a line extending in the first direction;
• a second semiconductor wafer comprising second semiconductor dies arranged in the first direction and the third direction, wherein each of the second semiconductor dies comprises a plurality of second test pad groups that each includes second test pads, the plurality of second test pad groups are arranged at positions respectively corresponding to positions of the plurality of first test pad groups, and the second test pads of each of the plurality of second test pad groups are electrically connected to each other through a line extending in the third direction;
• and
• a detector configured to determine a degree of accuracy in alignment between the first semiconductor wafer and the second semiconductor wafer, based on current flowing between the first test pads of each of the plurality of first test pad groups and the second test pads of each of the plurality of second test pad groups, with the first semiconductor wafer and the second semiconductor wafer being coupled to each other.