Chip assembly with shared testing and bumping pads

A method for making an integrated circuit die assembly, comprising:

• disposing a first IC tie at a topmost tier of an IC die stack, the first IC die comprising a first layout of shared contact pads disposed at a top surface of the first IC die;
• disposing a second IC die at a bottommost tier of the IC die stack, the second IC die comprising a second layout of shared contact pads disposed at a bottom surface of the second IC die, the first layout and the second layout being identical and the shared contact pads being configured for both contacting with a testing probe and bumping;
• coupling the first IC die with the second IC die;
• disposing a package substrate under the second IC die;
• and
• coupling the second IC die to the package substrate via the second layout of the shared contact pads.

A chip package comprising:

• a package substrate;
• a compute IC die mounted to the package substrate;
• and
• a memory stack die mounted to the package substrate and coupled to the compute die via routings formed in the package substrate, the memory stack comprising:
• a top IC die including a first layout of first shared contact pads arranged along a peripheral area of the top IC die, the first shared contact pads being configured for both contacting with a testing probe and bumping, the first shared contact pads including probe marks;
• and
• a bottom IC die having to a second layout of second shared contact pads, the bottom IC die electrically coupled to the top IC die directly or via one or more intervening IC dies, the second layout of second shared contact pads arranged identically to the first layout of first shared contact pads of the top IC die, the second shared contact pads devoid of probe marks.