Manufacturing method of semiconductor device and semiconductor device
AssigneeRenesas Electronics Corporation
InventorHideyuki TAJIMA
Life of this patent
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Abstract
A manufacturing method of a semiconductor device capable of improving the accuracy of overcurrent detection is provided. The manufacturing method of a semiconductor device includes a semiconductor wafer testing process includes a first testing process to determine the resistance variation rate of the replica resistor due to manufacturing variations when manufacturing the semiconductor wafer, and a setting process to determine the variation value of the reference current based on the resistance variation rate determined in the first testing process and set the current value of the current circuit to reduce the variation value.
Claims10
A manufacturing method of a semiconductor device, the method comprising:
- a semiconductor wafer manufacturing process in which a plurality of semiconductor chips, each having a power device and an overcurrent detection circuit that detects a current flowing through the power device, are arranged;
- a semiconductor wafer testing process for testing the semiconductor wafer;
- and
- a semiconductor device assembly process having dicing the plurality of semiconductor chips from the semiconductor wafer and assembling a semiconductor device equipped with the diced semiconductor chip,
- wherein the overcurrent detection circuit includes:
- a sense device through which a sense current proportional to the current flowing through the power device flows,
- a sense resistor connected between the sense device and a predetermined node,
- a reference resistor connected between the predetermined node and a current circuit, and
- a comparison circuit that compares the sense voltage generated in the sense resistor by the sense current with the reference voltage generated in the reference resistor by the reference current from the current circuit to form an overcurrent detection signal,
- wherein the semiconductor chip includes a replica resistor arranged adjacent to the sense resistor,
- wherein the semiconductor wafer testing process includes:
- a first testing process to determine the resistance variation rate of the replica resistor due to manufacturing variations when manufacturing the semiconductor wafer, and
- a setting process to determine the variation value of the reference current based on the resistance variation rate determined in the first testing process and set the current value of the current circuit to reduce the variation value.
A semiconductor device comprising:
- a power transistor;
- a sense transistor having a gate connected to a gate of the power transistor and a source connected to a predetermined node via a sense resistor;
- a reference resistor connected between a current circuit and the predetermined node;
- a comparison circuit that compares the sense voltage generated in the sense resistor by the sense current supplied from the sense transistor with the reference voltage generated in the reference resistor by the reference current supplied from the current circuit to form an overcurrent detection signal;
- a drive circuit that supplies a drive signal to the gate of the power transistor when overcurrent is not detected by the overcurrent detection signal;
- and
- a replica resistor arranged adjacent to the sense resistor,
- wherein the reference current supplied from the current circuit to the reference resistor is set to reduce the variation value of the reference current based on the resistance variation rate of the replica resistor caused by manufacturing variations.
Dependencies are inferred from the claim text.