Memory device

An integrated chip, comprising:

• a lower insulating structure arranged over a substrate;
• a lower conductor comprising a lower segment extending through the lower insulating structure and an upper segment extending outward from one or more sides of the lower segment to over the lower insulating structure;
• a passivation structure arranged along a lower surface and sidewalls of the lower conductor, wherein the passivation structure has a rounded surface that is above a top of the lower insulating structure and below the lower conductor;
• a switching structure over the lower conductor;
• and
• an upper conductor over the switching structure.

An integrated chip, comprising:

• a dielectric structure disposed over a substrate, the dielectric structure having an upper surface facing away from the substrate;
• a first conductive structure disposed between sidewalls of the dielectric structure and above the dielectric structure, the first conductive structure having an upper surface facing away from the substrate, the upper surface of the first conductive structure being more planar than the upper surface of the dielectric structure;
• a magnetic tunnel junction over the first conductive structure;
• and
• a second conductive structure over the magnetic tunnel junction.