Image sensor

An image sensor comprising:

• a first chip comprising a first substrate including a sensing region and a pad region and opposing first and second surfaces, a first interlayer insulating layer on the first surface of the first substrate and having first wiring patterns therein, and color filters on the second surface of the first substrate;
• and
• a second chip on the first surface of the first substrate,
• wherein the first chip comprises:
• in the pad region, a pad contact pattern, a connection electrode electrically connected to the pad contact pattern, and a connection contact structure electrically connected to the connection electrode;
• and
• in the sensing region, active contact plugs electrically connected to active regions of the first substrate, and
• wherein the active contact plugs and the connection contact structure are at a same level of the first interlayer insulating layer relative to the first surface, and have respective shapes that are tapered toward the first surface.

An image sensor comprising:

• a first chip comprising a sensing region, a pad region, and an optically black region between the sensing region and the pad region;
• and
• a second chip on one surface of the first chip, the second chip comprising circuits configured for driving the first chip,
• wherein the first chip comprises:
• a first substrate having opposing first and second surfaces;
• transfer gates on the first surface of the first substrate;
• an element isolation portion in the first substrate;
• a rear surface insulating layer on the second surface of the first substrate;
• photoelectric conversion portions laterally spaced apart from each other with the element isolation portion therebetween;
• a first interlayer insulating layer between the first substrate and the second chip;
• and
• first wiring patterns in the first interlayer insulating layer,
• wherein the second chip comprises a second substrate, a second interlayer insulating layer, and second wiring patterns in the second interlayer insulating layer on the second substrate,
• wherein the first chip further comprises, in the pad region, a pad contact pattern, a connection electrode electrically connected to the pad contact pattern, and a connection contact structure electrically connected to the connection electrode, and
• wherein the first wiring patterns comprise a connection wiring pattern that is nearest to the first surface, and the connection contact structure is electrically connected to the connection wiring pattern.