Image sensor and method of manfuacturing the same

An integrated chip comprising:

• a photodetector and transfer transistor on a first semiconductor chip and disposed along a first semiconductor substrate, on a second semiconductor chip and disposed along a second semiconductor substrate, or on a third semiconductor chip and disposed along a third semiconductor substrate, the transfer transistor including a first source/drain, a second source/drain, and a gate, wherein the first source/drain of the transfer transistor is coupled to the photodetector;
• a first pixel transistor on the first semiconductor chip and disposed along the first semiconductor substrate, the first pixel transistor including a first source/drain, a second source/drain, and a gate, wherein the first source/drain of the first pixel transistor is coupled to the second source/drain of the transfer transistor;
• a first lateral overflow integration capacitor (LOFIC) on the first semiconductor chip, the first LOFIC including a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode, wherein the first electrode is coupled to the second source/drain of the first pixel transistor by a first conductive interconnect on the first semiconductor chip;
• a first bonding pad on the first semiconductor chip and coupled to the second electrode of the first LOFIC by a second conductive interconnect on the first semiconductor chip;
• a second bonding pad on the second semiconductor chip, wherein the second bonding pad is bonded and coupled to the first bonding pad;
• and
• a second pixel transistor on the second semiconductor chip and disposed along the second semiconductor substrate, the second pixel transistor including a first source/drain, a second source/drain, and a gate, the second source/drain of the second pixel transistor coupled to a first reference voltage terminal by a fourth conductive interconnect on the second semiconductor chip, the first source/drain of the second pixel transistor coupled to the second bonding pad by a third conductive interconnect on the second semiconductor chip.

A method for forming an integrated chip, the method comprising:

• forming a photodetector and transfer transistor, the transfer transistor including a first source/drain, a second source/drain, and a gate, wherein the first source/drain of the transfer transistor is coupled to the photodetector;
• forming a first pixel transistor along a first semiconductor substrate of a first semiconductor chip, the first pixel transistor including a first source/drain, a second source/drain, and a gate, wherein the first source/drain of the first pixel transistor is coupled to the second source/drain of the transfer transistor;
• forming a first conductive interconnect on the first semiconductor chip and coupled to the second source/drain of the first pixel transistor;
• forming a first capacitor on the first semiconductor chip, the first capacitor including a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode, wherein the first electrode is coupled to the first conductive interconnect;
• forming a second conductive interconnect on the first semiconductor chip and coupled to the second electrode of the first capacitor;
• forming a first bonding pad on the first semiconductor chip and coupled to the second conductive interconnect;
• forming a second pixel transistor along a second semiconductor substrate of a second semiconductor chip, the second pixel transistor including a first source/drain, a second source/drain, and a gate;
• forming a third conductive interconnect on the second semiconductor chip and coupled to the first source/drain of the second pixel transistor;
• forming a second bonding pad on the second semiconductor chip and coupled to the third conductive interconnect;
• and
• bonding the first bonding pad to the second bonding pad, wherein the second electrode of the first capacitor is coupled to the first source/drain of the second pixel transistor by the second conductive interconnect, the first bonding pad, the second bonding pad, and the third conductive interconnect.